The present invention relates to fixed information content memories often referred to as read only memories (ROM) and more particularly to the programming of the underlying layers of random access memories (RAM) to perform as ROMS.
In certain situations it is desirable to be able to convert an existing static random access memory (SRAM) into a ROM using common underlayers. It is recognized that a memory cell initially designed as a ROM may be expected to be a simpler device than will be obtained when an SRAM is converted to a ROM. However there are situations where the ability to convert is extremely advantageous, for example, where the underlayer design of the SRAM has already satisfactorily passed various tests or has been approved for certain applications. An entirely newly designed ROM would have to be subjected to similar tests and possible design modifications and go through the approval process for the particular application. In addition, the conversion capability would allow a common inventory of partially fabricated wafers that include the underlayers to be utilized as either SRAMs or ROMs.
FIG. 1 is a schematic diagram illustrating one example of interconnections which can be used to convert the underlying layers of an SRAM to a ROM memory cell 6. M1 and M3 are P-channel transistors and M2 and M4 are N-channel transistors. The circuit is essentially an SRAM six transistor memory cell with the connection between the drains of M1 and M2 connected to a positive voltage, V.sub.DD, or a ground reference voltage, V.sub.SS, and the connection between M3 and M4 connected to either a positive voltage or a ground voltage. The specific connections are shown by the "1" or "0" designations in FIG. 1.
When the connections of FIG. 1 are made as shown for programming memory cell 6 as a "zero", transistor M1 has a positive voltage V.sub.DD and a ground voltage V.sub.SS across its source and drain connections respectively. Likewise transistor M4 has V.sub.DD and V.sub.SS across its source and drain, respectively. This has the potential of increasing the electrical overstress sensitivity of transistors M1 and M4. In addition transistor M1 now makes up a parasitic PNP structure connected directly across V.sub.DD and V.sub.SS . Also transistor M4 makes up a parasitic NPN structure connected directly across V.sub.DD and V.sub.SS.
FIG. 2 is a schematic diagram illustrating another example of interconnections which can be used to convert the underlying layers of an SRAM to a ROM memory cell 8. M1 and M3 are P-channel transistors and M2 and M4 are N-channel transistors. The circuit is essentially an SRAM six transistor memory cell with the drains of P-channel devices M1 and M3 disconnected permanently. The programming of memory cell 8 of FIG. 2 is accomplished by connecting the drain of transistor M2 to V.sub.SS for a "zero" memory state or connecting the drain of transistor M4 to V.sub.SS for a "one" memory state. The specific connections are shown by the "1" or "0" designations in FIG. 2. A disadvantage of the programming connections shown in FIG. 2 is that there is no active pull-up on the bit line that is to be driven to a high state. For example, when the circuit of FIG. 2 is programmed as a "zero" the bit line connected to the drain of M4 through pass-transistor M6 is intended to be pulled high, but transistor M3 is not available to perform the pull-up function. This will likely result in a slower read access time which may not be acceptable in certain applications.
Thus a need exists for a programming arrangement for converting existing SRAM underlayers to ROMs that does not have the disadvantages of electrical overstress sensitivity and provides active pull-up for the bit line that is intended to be pulled high.